Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level
نویسندگان
چکیده
منابع مشابه
Register-transfer level fault modeling and test evaluation techniques for VLSI circuits
Stratified fault sampling is used in RTL fault simulation to estimate the gate-level fault coverage of given test patterns. RTL fault modeling and fault injection algorithm are developed such that the RTL fault list of a module can be treated as a representative fault sample of the collapsed stuck-at fault set of the module. The RTL coverage for the module is experimentally found to track the g...
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Stratified fault sampling is used in register transfer level (RTL) fault simulation to estimate the gate-level fault coverage of given test patterns. RTL fault modeling and fault-injection algorithms are developed such that the RTL fault list of a module can be treated as a representative fault sample of the collapsed gate-level stuck-at fault set of the module. The RTL coverage for the module ...
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Due to the increasing complexity of modern circuit design, verification has become the major bottleneck of the entire design process. Most efforts are to verify the correctness of the initial Register-Transfer Level (RTL) descriptions written in Hardware Description Language (HDL).Major drawback of high level design methodologies such as RTL can be seen in the following facts. First, they lack ...
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ژورنال
عنوان ژورنال: International Journal of VLSI Design & Communication Systems
سال: 2011
ISSN: 0976-1357
DOI: 10.5121/vlsic.2011.2406